The invention relates to semiconductor devices and specifically to a varactor implemented using metal-oxide semiconductors.
A varactor is, essentially, a variable voltage capacitor. The capacitance of a varactor, when within its operating parameters, decreases as a voltage applied to the device increases. Such a device is useful in the design and construction of oscillator circuits now commonly used for, among other things, communications devices.
Of the various types of oscillator circuits currently in use, the so called LC oscillator offers the best combination of high-speed operation low-noise performance, and low power consumption. The operating frequency of an LC oscillator is normally controlled or tuned by varying the voltage across the terminals of a varactor. For such an application, a varactor should ideally have a high maximum to minimum capacitance ratio. This is because the capacitance range of a varactor, the difference between its maximum capacitance and its minimum capacitance over the full sweep of its control voltage, is proportional to the attainable tuning range of the oscillator. Thus, a large capacitance range means a much larger attainable tuning range of the oscillator. Such a wide tuning range allows the communication device using the oscillator to be more robust over a wide variation of components, temperatures, and processes.
Also ideal for a varactor is a large voltage control range. The varactor""s change in capacitance should occur over a large voltage range. Such a property allows the LC oscillator to be more immune to noise or small fluctuations in the control voltage.
A third desirable characteristic for a varactor is a linear voltage control range. The mathematical relation between a varactor""s input voltage and its capacitance should ideally be as linear as possible. In other words, a varactor""s capacitance-voltage reaction should be monotonic without gross non-linearity. By making the capacitance voltage characteristics as linear as possible, this reduces the AM to PM noise conversion in the LC oscillator in which the varactor is used. Not only that, but such a linearity also assists in maintaining the stability of a phase locked loop (PLL) in which the LC oscillator may be used.
Typically two varactor structures are used: the PN-junction varactor and the MOS varactor. Currently the PN-junction varactor is predominantly used in LC oscillators. Both these structures can be implemented using standard CMOS processes. The main drawback of the PN junction varactor is a low maximum to minimum capacitance ratio. This ratio is reduced further in deep submicron processes due to the higher doping levels needed in source/drain and well areas. The MOS varactor does not suffer on this account, with a high maximum to minimum capacitance ratio of roughly four to one for a typical 0.25 xcexcm CMOS process. Furthermore, the MOS varactor""s ratio increases in deep submicron processes due to the thinner gate oxide used. However, the MOS varactor""s transition from maximum to minimum capacitance is abrupt. This gives a MOS varactor a small, highly non-linear voltage control range.
What is therefore required is a varactor that has the advantages of a MOS varactor and without its drawbacks. Accordingly, what is sought is a varactor with a large maximum to minimum capacitance ratio and a large, generally linear voltage control range.
The present invention relates to a metal oxide semiconductor (MOS) varactor that takes advantage of the beneficial characteristics of MOS varactors to provide a high maximum to minimum capacitance ratio. By coupling in parallel at least one pair of MOS varactors with similar but shifted capacitance voltage (C-V) curves, the resulting capacitance is generally more linear while preserving the desirable large capacitance ratio. A pair of MOS varactors, one with a p+ type gate and one with a n+ doped gate connected in parallel approximates the desired result. However, by adding further varactor elements, with their threshold voltages shifted by either implanting specific properties in their bodies or by providing offset voltages, a more linear C-V curve is attained while preserving the desired capacitance ratio.
Accordingly, in one embodiment, the present invention provides a varactor comprising a varactor element pair, the element pair comprising a p gate varactor element and an n gate varactor element coupled in parallel, each varactor element having a structure chosen from the group comprising:
a) a body constructed out of a p type substrate; an n well implanted in the body; a gate contact; a gate insulator coupled between the gate contact and the body and electronically isolating the body from the gate contact; and two n+ regions of the body doped with n type impurities, said two regions being positioned on opposite sides of the gate insulator; and
b) a body constructed out of an n type substrate; a p well implanted in the body; a gate contact; a gate insulator coupled between the gate contact and the body and electronically isolating the body from the gate contact and two p+ regions of the body doped with p type impurities, said two regions being positioned on opposite sides of the gate insulator
wherein the p gate varactor element has a p type gate contact constructed to have p type properties, the n gate varactor element has an n type gate contact constructed to have n type properties, all n+ regions or p+ regions of both p and n gate varactor elements are coupled together to at least one voltage source, and all gate contacts of both n gate and p gate varactor elements are coupled together to an output and the voltage source is coupled to ground.
Another embodiment the present invention provides a varactor comprising a plurality of varactor elements coupled in parallel between an output and a voltage source, each of said plurality of varactor elements being chosen from a group comprising, a p varactor element having a p type gate and an n varactor element having an n type gate; each varactor having a body constructed of a p type substrate and having at least two n+ doped regions and a gate insulator electronically isolating the gate from the body wherein each gate is coupled to the output, each n+ region is coupled to the voltage source and the voltage source is coupled to ground.
Yet another embodiment of the present invention provides a method of extending a voltage control range of a varactor while maintaining a high maximum to minimum capacitance ratio of the varactor, the method comprising coupling in parallel at least one pair of varactor elements comprising, an n varactor element having an n+ doped gate, a p varactor element having a p+ doped gate, said gates being coupled to an output and n+ doped regions of bodies, said gates being coupled to a voltage source.